In a conventional CMOS imager, the active elements of a pixel cell perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) transfer of charge to the floating diffusion node accompanied by charge amplification; (4) resetting the floating diffusion node to a known state before the transfer of charge to it; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing pixel charge. Photo charge may be amplified when it moves from the initial charge accumulation region to the floating diffusion node through a transfer transistor. The charge at the floating diffusion node is converted to a pixel output voltage by a source follower output transistor.
Exemplary CMOS imaging circuits as well as detailed descriptions of the functions of various CMOS elements of an imaging circuit are described, for example, in U.S. Pat. No. 6,204,524 to Rhodes, U.S. Pat. No. 6,310,366 to Rhodes et al. and U.S. Pat. No. 6,326,652 to Rhodes, the disclosures of which are incorporated by reference herein.
A schematic view of an exemplary CMOS pixel three-transistor (3T) pixel cell 10 is illustrated in FIG. 1. The three transistors include reset transistor 32, source follower transistor 36 and row select transistor 38. A floating diffusion region 30 receives charge from a photosensor 25 and is connected to the source follower transistor 36 by a contact line 44 which is typically a metal contact line. The source follower transistor 36 outputs a signal proportional to the charge accumulated in the floating diffusion region 30 to a readout circuit when the row select transistor 38 is turned on. The reset transistor 32 resets the floating diffusion node to a known potential prior to transfer of charge thereto from photosensor 25. Photosensor 25 may be a photodiode, a photogate, or a photoconductor. If a photodiode is employed, the photodiode may be formed below a surface of the substrate and may be a buried p-n-p photodiode, buried n-p-n photodiode, a buried p-n photodiode or a buried n-p photodiode, among others.
FIG. 2 is a more detailed illustration of the source follower transistor 36 of the 3T pixel cell 10 of FIG. 1 as fabricated within a semiconductor substrate 16. As shown in FIG. 2, the source follower transistor 36 is formed in semiconductor substrate 16 having a doped well 20 of a first conductivity type, which for exemplary purposes is treated as a p-type. Field oxide regions 15, which serve to surround and isolate the pixel cell 10, are formed by any known technique such as thermal oxidation of the underlying silicon in a LOCOS process, or by etching trenches and filling them with oxide in an STI process.
A p-type blanket or masked enhancement implant may be conducted to implant p-type dopants at an implant dose of about 1×1011/cm2 to 1×1013/cm2 to help set the voltage threshold of the NMOS transistor to be built in the active areas. This implant is typically conducted after pad oxidation, prior to gate oxidation, or after polysilicon gate deposition.
Subsequent to the blanket enhancement implant and the formation of the gate stack of the transistor 36 of FIG. 2, a first implant is conducted to form lightly doped drain (LDD) regions 22 of the drain and source on either side of the gate stack of transistor 36. For NMOS devices, this light implant may be conducted with an n-type doping, typically a phosphorous or arsenic doping, preferably arsenic, at a dose concentration of about 1×1012/cm2 to 5×1013/cm2, more preferably 2×1012/cm2 to 1×1013/cm2. The first implant is self-aligned to the gate stack of the source follower transistor 36. This can be an angled implant at four orthogonal wafer rotations.
Next, a second halo angled implant is conducted to implant p-type dopants, for example boron or boron difluoride, adjacent the LDD regions 22 and to form halo implanted regions 25, as illustrated in FIG. 2. The halo implant is initially conducted on one side of the device. Upon completion, the device may be rotated 180 degrees and the halo implant process may then be repeated to form a halo implanted region 25 on the opposite side. In practice, the gate stack of the source follower transistor 36 may be subjected to four halo implants during processing. Four implants are typically performed because many of the transistors formed above the substrate are oriented at different angles relative to one another.
Sidewall spacers 35 are then formed and a heavier dose n-type implant is conducted to form low-resistivity source/drain regions 23 (FIG. 2) which merge with the lighter doped regions 22 and halo implanted regions 25. In NMOS devices, this heavier dose implant is an n-type implant, typically an arsenic implant, at a dosage of about 5×1014/cm2 to about 1×1016/cm2. This implant is self-aligned to sidewall oxide spacers 35 formed by known methods on the sidewalls of the gate stack of the source follower transistor 36. This n-type doping implant serves to convert a portion of the p-type region to an n-type region and also to form deeper n-type regions on either side of the transistor gate. The reset transistor of the pixel cell is similarly fabricated.
By employing the above-described angled halo implant and enhancement implant in addition to the LDD implant, short-channel effects are minimized, degradation in the threshold voltage is reduced, and the electric field is decreased to an acceptable level near the edges of the gate of transistor 36. More specifically, by “reinforcing” the p-type doping of the p-type well 20 of the semiconductor substrate 16 in the channel between the n-type doped LDD regions 22, the p-type doped angled halo implanted regions 25 improve the “threshold voltage Vt roll-off,” that is defined as the decrease of Vt as a function of the decrease in the gate length. Thus, short-channel induced effects such as drain/source leakage current when the transistor is switched “off” (i.e., “off-state” leakage) are reduced.
The above-described halo, enhancement and LDD implants provide a threshold voltage which, for the source follower transistor 36, limits the signal output swing which can be obtained from the pixel cell. That is, the maximum output signal is (VDD−Vt). Accordingly, the higher the Vt the lower the maximum signal swing. Thus, for example, if VDD=3.3 V and Vt=0.8 V, the maximum swing voltage of the source follower transistor 36 is limited to 2.5 V. Similarly, the higher threshold voltage Vt for the reset transistor 32 limits reset voltage which can be applied to the floating diffusion region 30. The resulting reduction of the maximum output swing of the pixel cell 10 due to the combined Vts of the reset and source follower transistors becomes (VDD−2×Vt), or 1.7 V.
As pixel cells are scaled down, it becomes more desirable to increase the maximum swing voltage for the source follower transistor and the maximum reset voltage applied to the floating diffusion region by the reset transistor. Lower threshold voltages for other pixel transistors may also be desirable.